AT49LV001N |
RFQ for AT49LV001N Required Field |
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| Technical/Catalog Information | AT49LV001NT-12JC |
| Vendor | Atmel |
| Category | Integrated Circuits (ICs) |
| Memory Type | FLASH |
| Memory Size | 1M (128K x 8) |
| Speed | 120ns |
| Interface | Parallel |
| Package / Case | 32-PLCC |
| Packaging | Tube |
| Voltage - Supply | 3 V ~ 3.6 V |
| Operating Temperature | 0°C ~ 70°C |
| Format - Memory | FLASH |
| Drawing Number | * |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | AT49LV001NT 12JC AT49LV001NT12JC |
| Product | Manufacturers | Pack | D/C |
| AT49LV001N | - | SSOP | - |
The AT49BV/LV001(N)(T) is a 3-volt-only in-system reprogrammable Flash memory. Its 1 megabit of memory is organized as 131,072 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 A. For the AT49BV/LV001N(T) pin 1 for the DIP and PLCC packages and pin 9 for the TSOP package are don't connect pins.
To allow for simple in-system reprogrammability, the AT49BV/LV001(N)(T) does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention.
Reprogramming the AT49BV/LV001(N)(T) is performed by erasing a block of data and then programming on a byte-by-byte basis. The byte programming time is a fast 50 s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections and two main memory blocks.
The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence.The 16K byte boot block section includes a reprogramming lock out feature to provide
Features |
| • Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV)• Fast Read Access Time - 70 ns• Internal Program Control and Timer• Sector Architecture One 16K Byte Boot Block with Programming Lockout Two 8K Byte Parameter Blocks Two Main Memory Blocks (32K, 64K Bytes)• Fast Erase Cycle Time - 10 seconds• Byte-by-byte Programming - 30 s/Byte Typical• Hardware Data Protection•DATA Polling For End Of Program Detection• Low Power Dissipation 25 mA Active Current 50 A CMOS Standby Current• Typical 10,000 Write Cycles |
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
